Spin transfer torque-magnetoresistive random access memory (STT-MRAM) is attracting attention as memory that uses a magnetic tunneling junction (MTJ) device, which is a memory device in which resistance can change. STT-MRAM is non-volatile memory capable of high speeds and rewrite tolerance close to that of dynamic random access memory (DRAM). Given these properties, various inquiries are being made regarding the use of STT-MRAM in high-speed memory such as cache memory and/or the like.
Memory cells that use MTJ devices (hereafter referred to as MTJs) include a 1T1MTJ configuration comprising one metal oxide semiconductor field effect transistor (MOSFET) and one MTJ. In this configuration, for example one end of the MTJ is connected to a bit line and the other end is connected to the drain of the MOSFET, which is a selection device. The MOSFET's source is connected to a source line, and the gate is connected to a word line. When a selection signal from the word line is input, the MOSFET, which is a selection device, turns on and an electric circuit connecting the source line and the bit line including the MTJ and the MOSFET is connected. Through this, current flows in the MTJ, and reading from or writing to the MTJ becomes possible.
The 1T1MTJ configuration offers the advantages that the area occupied by the memory cell is small so the configuration is suitable for high integration. However, the 1T1MTJ configuration poses the problems that output signals are small, high-speed sensing is difficult because a reference current (or voltage) is necessary, and access times are long. Consequently, there are cases in which a cell configuration with two MTJs arranged as a differential pair is employed.
For example, in FIG. 1 of Non Patent Literature 1, an example of a memory cell with a 4T2MTJ configuration (four transistors (MOSFETs) and two MTJs) is noted.
In addition, in FIG. 1(a) of Non Patent Literature 2, an example of a circuit with a 6T2MTJ configuration is noted. Moreover, in FIG. 8(a) of Non Patent Literature 2, an example of a circuit with an 8T2MTJ configuration is noted.
In addition, in Non Patent Literature 3, a different example of a circuit with a 6T2MTJ configuration is noted. This literature notes that the 6T2MTJ configuration can be utilized as secondary cache.
When configuring the STT-MRAM, arranging memory cells having a differential pair configuration as described above in a matrix shape is necessary. However, when memory cells are arranged in a matrix shape, the problem exists that sub-threshold current (weak inverted current) from the driving MOSFET flows to the MTJ, and a leak current is generated. This leak current is multiplied in accordance with increases in the number of memory cells.
To cope with this problem, a gating method that interrupts the supply of the power source to this circuit is employed during the time when the circuit is not active.
There are a variety of methods of power gating. For example, in two-dimensional power gating (coarse power gating), a power line driver is positioned for each subarray including a plurality of memory cells. One power line driver controls the power source supply to the plurality of memory cells included in the assigned subarray.
In addition, with one-dimensional power gating (fine power gating), power drivers are assigned to each row (or column) of a memory cell array. One power driver controls the power source supply to memory cells arranged in the corresponding row (or column).
When the same number of memory cells is arranged, fine power grating uses a larger number of power drivers than coarse power grating, so the area monopolized by the circuit becomes larger. When the number of power drivers is simply reduced in order to lessen the area monopolized by the circuit, effects emerge such as wake up time becoming slower and operating current becoming larger, and these have an ill effect on memory performance.